Toshiba has developed a new flip-flop circuit using 40nm CMOS process that reduces power consumption in mobile equipment.
The new flip-flop circuit temporarily stores one bit of data during arithmetic processing by a digital system-on-a-chip (SoC) incorporated in mobile equipment and other digital equipment.
Toshiba said that it has changed the structure of the typical flip-flop and eliminated the power-consuming clock buffer, and has added adaptive coupling circuitry to the flip-flop to avoid data collision between the data writing circuitry and the state holding circuitry.
In addition, the combination of an nMOS transistor and a pMOS transistor adaptively weakens state-retention coupling and prevents collisions.
Further, the company said that despite the addition of the adaptive coupling circuitry, overall simplification of the basic flip-flop configuration reduces the transistor count from 24 to 22, and the cell area is less than that of the conventional flip-flop.
