IBM Corp machines based on the forthcoming high-end Rios 2 multichip set could be on the market by the middle of this year, according to IBM sources. The existence of Rios 2 as a separate development from the IBM-Motorola Inc-Apple Computer Inc collaboration on Rios 1 or PowerPC, was confirmed at IBM’s extension of the RS/6000 line last month. Two lines of development are necessary if IBM is to keep the performance of the Rios RISC competitive at the same time as extending the range downwards with the single chip PowerPC, the company says and Rios 2 will drive forward both the integer and floating point performance of Rios, adds IBM. Rios 2 is described as a next-generation superscalar RISC with single branch, dual fixed point and dual floating point units. It will be able to execute up to six instructions (or eight operations) per clock cycle (compared with the PowerPC’s four instructions or five operations). There will be new instructions for floating point, SQRT and convert to integer, and improvements to increase cache and memory bandwidth and reduce transaction latency. Initial implementations are not expected to be 64-bit – that should first appear in the PowerPC 620 chip, expected next year. IBM insists that, despite the implementation differences, binary compatibility between Rios 1 and Rios 2-based systems will be maintained, although some re-compilation may turn out to be necessary to take full advantage of new performance features. It is not yet clear whether Rios 2 will be offered to IBM’s PowerOpen partners, other than those that specifically take IBM RS/6000s as an OEM product, such as Compagnie des Machines Bull SA and Wang Laboratories Inc. An IBM source said it would be interesting to see how Hewlett-Packard Co, currently winning the performance race over Rios with its PA 7100 chip, will respond to the announcement – what do they say about Hubris and Nemesis…
