DEC bets the company on its $1,000m Alpha RISC development effort, opens it to all

Digital Equipment Corp has been selectively leaking details of its Alpha project since last October, so it was no surprise that little new came from the official announcements last week. In Europe, DEC hosted an event at its South Queensferry fabrication plant, nestling under the shadow of the Forth Bridge in Scotland – which along with the Hudson, Massachusetts facility will be producing the chips. The announcements covered three areas. First, the Alpha architecture, which is full 64-bit, open to any operating system or language (including Open VMS, OSF/1, and in the future NT and real-time operating systems), and scalable to 1,000 times its initial iteraton (with the help of multi-processing). Second, the initial product, the 21064 running at 150MHz, sampling immediately and shipping by mid-year. Third, a newly inaugurated open business practice, described as fundamental departures from DEC’s conventional ways of doing business – namely the licensing of Alpha to other semiconductor partners; the licensing of the manufacturing and design of the chip, allowing copies of Alpha built in accordance to DEC’s design rules, the licensing of DEC software to any Alpha partner; sales at chip, board and system-level; and customer and OEM support from DEC to Alpha users.

Cray, Kubota will be the first of many to sign up to use the Alpha RISC

Cray Research Inc did little to elucidate its reasoning for choosing the Alpha chip for its first-generation massively-parallel computer, saying only that its 64-bit architecture and high clock speed made it very suitable for the purpose. Cray spokesman John Fleming pointed out that the chip was of similar power to the 15-year-old Cray-1, and that, due to the large numbers of chips per system, Cray was likely to be the first to get volume discounts from DEC. The Sparc project, based on the assets of acquired Floating Point Systems, would address a different market, he insisted. Kubota Co Ltd, the second vendor partnership to be announced, says it plans to use Alpha for its next-generation Titan graphics multi-processors, which come from the now-defunct Stardent Computer Corp. These currently use the MIPS chip. The company is already well-under way with a new modular graphics and imaging sub-system that can be field-installed in the existing 1,000 or so Titans installed, or used with the new systems. They will run the OSF/1 operating system. Kubota hopes to show the first results of its Alpha and graphics work at the Siggraph show this July, and is promising customer shipments by the end of this year. Kubota was attracted to Alpha by the performance claims, by its durability, and its support for TurboChannel. It says it will continue to offer and develop MIPS-based Titans, and will provide migration and integration services for customers using both or migrating from one to the other. Santa Clara-based Kubota Pacific, which has responsibilities for marketing the Titan range outside the Far East, last month pre-announced a MIPS R4000-based workstation. It also builds systems to MIPS’s specifications for sale in Japan. Many other announcements are expected over the next few weeks, said Pier Carlo Falotti, although there are still details to work out over the (probably two) semiconductor fabrication partners DEC wants.

Alpha adds third processor option to ACE

Will the Advanced Computing Environment initiative be strengthened or wrecked by the Alpha announcement? DEC doggedly insisted on the former, while the 100-plus European journalists shipped out to Queensferry mostly thought the latter. The independent industry analysts, caught between a rock and a hard place, reluctantly agreed that it looked bad for ACE, and also said they expected to see DEC offering incentives and migration aids for its current MIPS users as well as VAX users something that didn’t quite square with DEC’s insistence that the MIPStations would not be affected by the new machines. Pier Carlo Falotti said that the addition of

Alpha as an ACE machine would increase the options for ACE users – and he hinted heavily that Microsoft’s NT would be included in forthcoming Alpha announcements. When asked if DEC had effectively highjacked ACE for its own ends, Falotti said if you adhere to the standard, you are part of ACE – you don’t have to ask permission. Alpha adheres to ACE. Once a means of extending a persoanl computer-like architecture to new-generation technology, ACE now has two 64-bit RISC chips competing for that business, along with a newly-aggressive Intel Corp keen on keeping its existing business, plus at least three operating systems (it did not emerge whether VMS would be offered as an alternative ACE operating system – but why not?) As for MIPS Computer Systems itself, Falotti said DEC would be keeping its 5% stake, and insisted that it would be in trouble if MIPS, currently struggling, did not survive the extra competition.

DEC maps out Alpha’s future with advanced CMOS, GaAs versions planned

Following the VAX is no easy task – and DEC has pulled out all the stops to come out with a technological development it hopes will last it for the next 25 years. The path was not easy – DEC has been researching RISC since 1982, and first showed off a 32-bit processor running at 50MHz in 1989. This project was shelved, only to bounce back as the 64-bit Alpha. Implemented in DEC’s fourth-generation 0.75 micron CMOS, the chip has a transistor count of 1.68m devices, using three layers of metal and a 3.3 Volt power supply. DEC says it is running 200MHz versions in the labs – which according to senior consulting engineer Dan Dobberpuhl is six to 18 months ahead of the industry in working at this level of complexity with today’s technology. DEC has a 10-year road-map set out for the chip, which includes CMOS 5 and CMOS 6 versions running at 275MHz plus, with CMOS 6 and 7 versions towards the end of the decade. Aside from the main design team there are two more groups, one thought to be working on a Gallium Arsenide version running at up to 1,000 MIPS, and the other working on lower price, lower power-performance designs. There are 500 people in the semiconductor engineering group. Dobberpuhl claims to have learned lessons from the other RISC chips on the market, which are now on average 10 years old or so. They carry artifacts to the technology of the day, which are becoming big liabilities, he said. Branch delay slots, for instance, are a liability for superscalar operation, and DEC does not have to rely on the condition codes included the condition codes that appear in other RISCs. The single chip 21064 is a full 64-bit, super-scalar and super-pipelined implementation, with 64-bit integer and floating point units and related addressing units. There are 8Kb instruction and data caches with cache bandwidth of 3.2 Gigabytes-per-second. External cache extends to 8Mb. The major problem with Alpha at the moment is price – you can get a whole Hewlett-Packard workstation for the price of the Alpha chip commented one observer at the launch. – John Abbott