Cray Research Inc is this week due to launch its Digital Equipment Corp Alpha RISC-based entry into the massively parallel fray, having delivered a 32-CPU prototype to the Pittsburgh Supercomputing Centre at the beginning of the month. At Pittsburgh, it is said to be meeting all of its performance expectations and is reported to have the best bandwidth capability of the massively parallel systems currently on the market. However, Electronic News reports that the news is not all good: it says Cray has not yet decided whether to use Alpha for its its second-generation massively parallel systems and is using an architecture that enables it to keep its options open it already has one foot firmly planted in the Sparc camp. Despite the fact that Cray was trying to keep the thing under wraps, Electronic News managed to get under the hood, and finds that the prototype Alpha system, code-named TD3, uses a three-dimensional torus interconnect topology to increase bandwidth. As with the Inmos International Ltd, each switch node operates bi-directionally in each dimension to minimise network distances, and there are two 64-bit Alpha AXP processors and one switch in each node so that a 64-node machine has 128 processors. The switches – which have 12 paths through them since each link is cocurrently bi-directional – talk node to node rather than to other switches so that a processor at one end can only talk to one at the other by going via the intervening nodes – but in practice, the three-dimensional cubic arrangement means that all distances are short, and in a four-by-four-by-four node cube – 64 nodes – the maximum distance between any two nodes in any direction is two nodes. The interconnect switches are derived from the logic that links processors to memory in Cray’s vector processors. The company plans to market the parallel machines as adjuncts to its vector processors, connected to the Y-MP system by high-speed channels. The Y-MP and T3D will share a common input-output subsystem off which hang disks, tapes, workstations and networks. The idea of combining the two is to run each part of the application on the more appropriate processor – parts of an application have no parallelism at all, and according to the nature of a user’s work, the ideal may be a large T3D and a small Y-MP or vice versa. The machine will need to be water-cooled, and Cray is differentiating it from the generality of parallel machines by stressing the exceptional bandwidth and speed of the interconnect technology.
