By Timothy Prickett Morgan
The Pulsar chips due to appear on September 12 with IBM Corp’s revamped RS/6000 workstation and server lines (see Top Stories ) will use IBM’s 0.22 micron CMOS-7S copper chip fabrication process rather than the 0.35 micron CMOS-6S2 process used in the Northstars. Other than that, there are only minor differences between the two chips. The Pulsar will have two integer units and a floating point unit capable of processing one floating point operating per cycle, just like Northstar. IBM is still not being specific about how much L1 and L2 cache memory will be included with the Pulsar or its clock speed. By being vague, IBM has some wiggle room in case the 24-way SMP ratios don’t pan out as it expects; if scalability is not up to snuff, it can crank up clock speeds a little to compensate. Odds are that the Pulsars will have 128Kb of L1 data cache and 128Kb of L1 instruction cache, double the amount on the current Northstar chips. If the Pulsars have external L2 cache, sizes should range from 8Mb to 12Mb, and if the L2 cache is integrated on the Pulsar chip – as IBM expects to do with the Power4 dual CPU microSMPs due in 2001 – L2 caches could be as small as 6Mb to 10Mb. Pulsar clock speeds could be anywhere from 450MHz to 525MHz, with 450MHz looking likely.
The current fastest Northstar chip, used in the RS/6000 H70 server, runs at 340MHz. The IBM copper process allows chips to be cranked up by about 30% compared to aluminum CMOS processes, and that brings the Pulsar in at 450MHz. Moreover, the I-Star follow-on to Pulsar, due early next year in AS/400e servers based on the Condor box, are expected to use copper and silicon-on insulator processes and run at 560MHz. SOI yields about 25% more clock cycles to a chip design, and if you start Pulsar out at 450MHz and add SOI, you get 560MHz. That said, the Pulsar could run faster just because IBM can make it go faster. If not, IBM knows it has I-Stars available in early 2000. IBM has not said it will use the I-Star processors in RS/6000s yet, but it probably will to keep pace with the HP PA-8600s and the Sun Cheetahs. That would make the Pulsars very short-lived, like a 450MHz Pentium III Xeon was this year.
The Condors are expected to include so-called smart caching algorithms implemented in silicon that IBM has been testing in various AS/400s and RS/6000s and that it needs to perfect for the forthcoming Power4 microSMPs. IBM has also suggested that it has a few SMP tricks up its sleeve and that it will have better SMP ratios that it has been able to attain with past generations of RS/6000s. The new AIX, version 4.3.3, that runs on the S80s will also have performance enhancements. It looks like about 65% of the increased scalability in the S80s over the S7As will come from faster processors and double the main memory (at least 64Gb, and maybe even 96Gb on the biggest Condors). Another 25% of that power tripling will come from going from 12 to 24 processors in an SMP cluster and another 10% will come from changes in AIX 4.3.3. At triple the current performance, IBM should be able to push the Condors to over 100,000 TPM on the TPC-C online transaction processing benchmark test, which puts Condor in the same power class as the fastest Sun Starfires, HP V2500s and Sequent NUMA-Qs.
Perhaps more significant for IBM’s commercial RS/6000 customers is the fact that the Pulsar’s engine speed is about 70% faster than the Northstar chip used in the S7A, and engine speed is the single greatest factor in reducing batch workload runtimes. This is much more important than scalability for most midrange customers, and the faster engines will be a welcome relief.
In addition to the S80s, IBM will also probably revamp the new H70 line, upgrading its Northstar processors with Pulsar chips. By doing so, IBM will fill in the gap between the six-way Condor and give customers the option of having smaller Pulsar machines. The current H70 has a TPC-C rating of just over 17,000 TPM. Moving from 340MHz to 450MHz processors would boost server scalability in the new machine, probably to be called an H80, by about 33% to 22,500 TPM. That’s not a big increase, but if IBM can charge the same amount for the faster H80, it can show price/performance improvement without hurting H series sales, which have been one of the bright spots in the RS/6000 line in 1999.
The word we hear is that IBM will also announce the new Nighthawk nodes for its RS/6000 SP parallel supercomputer line. Over the past few months, IBM has cautioned Unigram.X about tying the Power3-II chip announcement to the S80 and Nighthawk announcements, but IBM may have been able to get the Power3-II technical processing chip out the door in time for the September 14 announcements after all.
The current Winterhawk SP nodes have one or two 200MHz Power3 processors, each of which is able to process four floating point calculations per cycle. The Power3-II chip is a copper shrink of this chip that could run at anywhere from 50% to 100% faster than the Power3 chip, or from 300MHz to 400Mhz. The Nighthawk SP node, which could use Power3 chips unless the Power3-II chip is ready, will have from 2 to 8 processors on a single node. RS/6000 SP customers with single or dual processor nodes will be able to radically consolidate their frames by moving to Nighthawk, whether or not the faster chip debuts this year. Given the fact IBM’s workstation people will be at the announcement, it seems likely that Power3-II will be announced in September as well. IBM’s original plans called for it to deliver not only the Nighthawk Power3-II SP nodes in October, but also new four-way Power3-II workstations and servers for the low end of the technical processing market.
