There have been whispers going around for a couple of years now that Sir Clive Sinclair was working on a magic new chip that would emulate the Intel iAPX-86 and other environments using RISC techniques, and run software blindingly fast. Now a few more details have emerged: according to Electronic World News, a company called PgC Ltd will be marketing the chip, which will be rated at about 200 MIPS and cost about $400. To emulate existing microprocessors, the PgC 7600 treats their instructions as data and translates them into its own native code – a technique similar to that planned by Champaign, Illinois-based Teraplex Inc with its minimum instruction set technology (CI No 1,627). In that mode it is claimed to offer the performance of a 12MHz 80286 box. It is being fabricated in GEC Plessey Semiconductors Ltd’s low-power bipolar collector diffusion isolation process, which supports high clock speeds and gives high yields. And with just 90,000 transistors on a 10mm by 10mm die, it is not a complex chip to fabricate. The part is designed to be used both in mass market personal computers, and in multiprocessors using dual-ported RAMs to provide a 1.28Gbps bandwidth for connections to other processors. The part is also self-clocking, starting a new instruction as soon as the last one is executed, which means an instruction can be executed every 5nS, nominally equivalent to a clock speed of 200MHz if the thing had an external clock. The dual-ported memory will be able to pass object-oriented data structures in a way similar to the packet data structure used in dataflow computers. In order to interface the chip to memory so as not to lose much of the speed benefit in memory accesses, the part has a bank of 40 32-bit data registers on chip, and a pre-fetch cache for 32 instructions. It also has on-board memory and interrupt controllers and timer for memory synchronisation. The Harvard Architecture RISC also includes 768 bytes of ROM for storing a library of complex instruction set subroutines to facilitate emulation of parts like the 80386 and the Motorola 68020. Extending Sir Clive’s commitment to waferscale technology, the designers believe that by going to finer design rules it will be possible to fabricate more than one processor on the same chip – monolithic 10-processor chips are in the plan, with associated on-chip dual port memory. PgC plans a $40 80 MIPS CMOS version of the part next year and a $100 250 MIPS single processor bipolar part. And in the middle of 1993, a 1,000 MIPS CMOS PgC7700 with 512Kb of on-chip memory is planned at around $400. A bipolar version with less memory but rated at 2 GIPS and costing $200 is also in the plan. As well as being the basis of low-cost hand-held and desktop computers, the des igners hope the chip will find emb edded applications such as X-termi nal control, other graphics applic ations, and in telecommunications.
