Silicon Graphics Inc says it has had working versions of its high-speed Spider symmetric multiprocessing interconnect and network switch for two months now (CI No 2,927). Spider – Scalable Pipelined Interconnect for Distributed Endpoint Routing – is being targeted for use in a large-scale Silicon Graphics system arrangement previously identified as Lego, although Silicon Graphics chief technical officer Forrest Baskett says we are not allowed to call it that any longer (CI No 2,866). Silicon Graphics claims no software changes will be required to take advantage of Spider. Whether it will be made available for tying together existing Silicon Graphics Challenge server configurations apparently has yet to be decided. Silicon Graphics claims that Spider is an order of magnitude ahead of existing interconnect-switch technologies; Spider supposedly has a bandwidth of 800Mbps per device and a point-to-point latency of 330 nanoseconds (CI No. 2,927). Although Spider is said to share functionality with Silicon Graphics’ other high-end interconnect, the T3E mechanism it picked up with the acquisition of Cray Research Inc, there doesn’t appear to be a move to create a unified interconnect like it is doing with other items such as the Irix and Unicos operating systems.
