Motorola Semiconductor Group’s High Performance Embedded Systems Division has been outlining an embedded microprocessor RISC architecture, ColdFire, designed from the ground up for applications resulting from the convergence of computers, communications and consumer electronics. The company claims ColdFire combines conventional 32-bit RISC techniques but executes a single instruction per cycle, with a variable-length instruction set whose operations are defined by one, two or three 16-bit words. The operations have been implemented using the machine language syntax of Motorola’s MC68000 embedded technology. As such ColdFire supports development tools already targeted for its embedded MC68000 lines. ColdFire, which Motorola calls a VL RISC, consists of a two-stage instruction fetch pipeline, a two-stage operand execution pipeline and a first in-first out instruction buffer to decouple the two pipelines. The company says using a variable-length RISC instruction set enables it to achieve significant code density advantages over conventional fixed-length RISC processors that restrict machine language instructions to the same size. Each fixed-length instruction has a minimum length, typically 32 bits, so simple instructions take up as much memory space as advanced instructions, resulting in higher memory requirements and larger compiled code, it says. ColdFire’s variable-length design, which supports instructions of different lengths, enables code to be packed more efficiently in memory. It is due out next year.
