Synopsys has expanded the SATA IP portfolio by introducing the SATA PHY IP for the SMIC 130-nm technology, therefore enabling a SATA service, which also includes the AHCI host and device digital controllers as well as verification IP. Accessing all the IP from one provider allows designers to lower the risk and cost of integrating SATA interfaces into their high-performance system-on-chip (SoC) designs.
According to the company, the DesignWare SATA PHY IP substantially exceeds the SATA electrical specification in areas such as jitter, margin and receive sensitivity, thus delivering a robust design without sacrificing performance. The advanced built-in diagnostic capabilities provide customers with an on-chip sampling scope for quick debug of the PHY.
The PHY also comes with ATE test vectors which enable at-speed production testing of the PHY. Additionally, the DesignWare SATA PHY IP relies exclusively on standard digital CMOS process technology and does not require special process options, which results in significant manufacturing cost reduction and ease of integration into a SoC, said Synopsys.
John Koeter, vice president of marketing for solutions group at Synopsys, said: With the release of the DesignWare SATA PHY IP designed for SMIC 130-nm technology, Synopsys continues to provide designers with the IP they need in the required foundry process. Synopsys is addressing key concerns that our customers are facing today by characterizing the PHY to help ensure it meets and exceeds the SATA specification and passes SATA-IO compliance, thereby providing customers confidence that our PHY is fully interoperable with other SATA products.