Synopsys has introduced its complete DesignWare IP service for PCI Express (PCIe) 3.0. PCI Express 3.0 is the PCI Express I/O standard, which is currently under development within the PCI Special Interest Group at a preliminary revision 0.5.
The company claims that DesignWare IP enables integration of the 8.0 GT/s PCI Express 3.0 interface into system-on-chips (SoCs) for enterprise computing applications. Built on the DesignWare IP for PCI Express 2.0 and 1.x architecture, which has been silicon-proven in SoC designs, the DesignWare IP for PCI Express 3.0 allows designers to incorporate the new PCI Express 3.0 features into their products.
John Koeter, vice president of marketing for the solutions group at Synopsys, said: The enterprise computing market is driving the need for the high-performance PCI Express 3.0 interface in the products our customers expect to be shipping in 2010. By providing designers with early access to PCI Express 3.0 IP that is based on a proven and trusted architecture, Synopsys lowers the risk of incorporating the PCI Express 3.0 interface into advanced SoCs.
The company said that its development methodology helps ensure the new DesignWare IP offering to provide the same level of interoperability and adherence to the PCI Express standard compared to the existing DesignWare IP for PCI Express products.
According to Synopsys, its suite of digital controllers for PCI Express 3.0 is based on the DesignWare IP for PCI Express 2.0/1.1 architecture, providing designers with small area and low latency to improve overall system performance. The DesignWare digital controllers for PCI Express 3.0 implement the same interfaces as PCI Express 2.0, allowing customers to upgrade to PCI Express 3.0.
The company noted that the DesignWare Verification IP for PCI Express 3.0 supports directed testing and constrained random methodologies defined in the Verification Methodology Manual (VMM) for SystemVerilog and allows designers to create protocol test scenarios for verifying their SoCs.
