Synopsys has unveiled its Discovery Verification IP (VIP) family based on the new VIPER architecture.
Written entirely in SystemVerilog with native support for the UVM, VMM and OVM methodologies, the company said the new solution can speed and simplify verification of complex system-on-chip (SoC) designs.
The new software includes Protocol Analyzer, a protocol-aware debug environment which enables engineers to understand, identify and debug protocols in their designs.
Synopsys Verification Group senior vice president and general manager Manoj Gandhi said protocol verification had become a critical part of SoC verification, with major implications for cost and time to market.
It supports all major simulators offering enhanced performance and configuration, coverage and test-development capabilities to improve IP and SoC designers’ productivity, the company said.
Synopsys VIP is available for a broad portfolio of protocols including USB 3.0, ARM AMBA AXI3, AXI4, ACE, HDMI, MIPI, Ethernet 40G/100G, PCI Express, SATA, OCP and many others.
Synopsys’ Protocol Analyzer, available in the Discovery VIP family, offers protocol-centric debug allowing engineers to understand protocol activity, identify bottlenecks and debug unexpected behaviour.
Based on Synopsys’ new VIPER architecture, the new software can track protocol-centric simulation information to provide protocol-level analysis views with timelines synchronised to RTL waveforms and other views.
