Sun Microsystems Inc duly fleshed out the roadmap for its UltraSparc RISC disclosed here a couple of weeks back (CI No 3,472), and, as expected, says it will ship an ‘S’ series UltraSparc V chip for use high-end servers in 2002 running at 1.5GHz and produced in Texas Instruments Inc’s copper-with-xerogel process. Mid-range processors with on-board support for PCI bus and designated the ‘I’ series will be calved from the high-end parts and at the low-end the 32-bit microSparc architecture is melted down in favor of a new ‘E’ series designed for use in embedded systems culled from the ‘I’ implementation. It usually takes 12 months after chips become available before system-level implementations are delivered – slightly less in the case of embedded designs – but given Sun’s not got an E series embedded design on the roadmap until the end of the year, we wonder how long it’ll be before 64-bit JavaStations will see the light of day given their current 32-bit incarnation has no future. Moreover, though Sun has retained TI as its series foundry for the S series, it would only say that I series parts up to and including the 480MHz US-IIi+ implementation due by mid-1999 will definitely be built by TI while a foundry for the low-end part has not been identified. Candidates include Fujitsu Ltd and LSI Logic Inc, which fabbed microSparcs, and MIPS foundry NEC Corp, which was lined up to make the microSparc IIIe which never saw the light of day. Sun has identified 300MHz USe-300, 400MHz USe-400 (year-end 1999) and 500MHz USe-500 (year-end 2000) CPUs. First 600MHz US-IIIs ‘Cheetah’ silicon done in TI’s 0.18 micron process will ship by year-end (US-II will also be cut in 0.18 microns this year), around a quarter or so behind the schedule Sun had been touting for 18 months or more. It’s due in new high-end Sun servers by the end of next year. The 16m transistor US-IIIs uses a new pipeline architecture and requires a higher-speed version of the Ultra Port Architecture system bus – currently running at 120MHz – meaning users will need to box-swap to systems with the new bus to take advantage of US-IIIs’ performance. Following a 750MHz rev mid-2000 is the 1GHz US-IVs due by the end of 2000, which will be built in TI’s 0.15m process with the same basic pipeline technology as US-IIIs. The post-2001 1.5GHz, 50m transistor US-Vs will utilize a completely new 64-bit pipeline. There’s enough mileage on the roadmap between US-IVs and US-Vs to add some speed bumps which, the company claims, will keep it on par or ahead of Merced’s performance. Because Intel Corp’s timescale is so unclear, Sun says it can’t predict at which point UltraSparc will need go-faster stripes. Sun says each odd-numbered UltraSparc generation will come with a new pipeline technology; even numbers designate new process technology. The 480MHz US-IIi+ due by year-end will be followed by the SMP-enabled US-IIIi mid-2000 and a 700MHz US-IIIi+ by the end of 2000. The 1GHz US-IVi is due before the end of 2001. At the Java end of the scale, Sun’s Pico Java Core has been licensed to C-Cube (also an embedded Java licensee), IBM, Hyundai, LG, NEC, and Fujitsu.
