Engineers at the Philips Research and Development Centre, part of Philips Components-Signetics, Sunnyvale, California, have developed a microprocessor architecture called LIFE, for Long Instruction Format Engine, using an improved form of Very Long Instruction Word technology, using 100 or more bits per instruction word, which does away with the need for object code compatibility and makes it suitable to be used as a high performance engine for embedded control applications. The architecture was described in a technical paper at the International Solid State Circuits Conference in San Francisco by researchers, Labrousse and Gerrit Slavenburg, who led the two and a half year long design effort.
50MHz clock
The 50MHz, 32-bit single chip device has been implemented with a 1.5 micron double metal CMOS process using electon beam direct write on wafer lithography. The chip comprises 77,000 transistors, on a total chip area of 78 square millimetres, contained in a 224-pin pin-grid array. Philips say that Very Long Instruction Word architectures outperform complex and reduced instruction set and even Super-Scalar architectures for a given technology. The first silicon, designed for a 50MHz clock, is currently running on a prototype board at 32MHz and according to simulations and early results, Philips claims that the chip reaches 60 to 100 VAX MIPS for standard integer applications by using resource parallelism, pipelining and conditional execution. That is two or three times the performance of Motorola’s new 68040 and MIPS Computer Systems Inc’s R3000, claims Junien Labrousse, one of the researchers. The chip is still under evaluation and several benchmarks are running at present. Though very long word architectures have been explored for high performance processors and computers over the past few years, there has been a problem in the integration of such architectures. But Philips Components-Signetics believes that this type of architecture is now rapidly gaining recognition in the race for high performance in general-purpose processing. The company believes that it will complement the embedded Sparc controllers that it plans to develop as part of an agreement with Sun Microsystems. Target applications for these high performance engines are expected to be in image processing, speech recognition, robotics and other embedded systems, primarily in military markets and data processing. For example, when used in conjunction with an embedded Sparc processor, the high-performance engines built with LIFE architecture could serve as a graphics accelerator. Marketing manager Shlomo Waserol believes this would bring imaging and graphics capabilities to low-end workstations. The single-chip processor can be used either as a stand-alone central processing unit, or much like Intel’s 80860 RISC processor – but it does not support floating point operations. The physical interface is based on a 32-bit data bus controlled by a 28-bit address and a 200-bit instruction bus, multiplexed in two half-words of 100 bits each, controlled by a 21-bit address. The resulting instruction pad cycle time is 10nS. –
By Elvadia Tolputt
The LIFE chip consists of several independent functional units. Two identical 32-bit arithmetic-logic unit, a 32-bit data memory interface, a register file, a constant generation unit and a branch unit. These units are pipelined. All stages operate in lock step and are controlled by a global clock. The independant units are controlled on a cycle by cycle basis by the 200-bit instruction bus. The units are connected to a shared on-chip multiport memory from which they take their operands, and into which they write results. Any previously computed result can be used as any operand of any unit. Ideally six native operations can be initiated every cycle, but in reality unit utilisation depends on the fine-grain parallelism provided by the applications. Except the constant unit, each unit gets an extra Boolean operand from the multiport memory. This will control whether the operation scheduled on the unit completes, and if the
operation has any side effect on the processor state. All these operands are independant and when efficiently used by the compiler will drastically reduce the effect of branch delays. A special design was required to achieve the necessary bandwidth out of the multiport memory. Each operand of each unit has a local storage unit called a funnel file. Funnel files have separate read and write ports and the addresses of these ports are directly controlled by a field of the instruction. A multiplexer in the write port selects which unit’s output will be written in the corresponding funnel file. The functionality of such an implementation is very close to an ideal multi-port memory. The Compiler for Regular Architecture, CREATE, provides a generic compiler that allows for long instructions and generates nearly optimal code for a variety of languages and core functions. Power consumption is of the order of 2W at 50MHz. Philips Components-Signetics doesn’t plan to offer the chip as a general purpose processor but as a basis for customer-specific integrated circuit offerings. For this, the core will be expanded so that functional units, such as real-time interfaces, multiplier-accumulators and bit manipulators can be integrated. Some periphery, such as analogue-to-digital conversion capabilities may be added. Initially customer-specific integrated circuits are expected to be marketed to several dozen companies. Eventually application-specific integrated circuits may be offered to broader industry segments. A fully customiszed high-performance engine would contain up to several hundred thousand transistors on a die no more than 100 square millimetres.
Embedded systems
According to Labrousse, a customer meeting financial requirements and placing an order would receive the product by the end of this year. In target embedded systems applications, where volumes are expected to be a minimum of 10,000 units, unit price of such a device would be between $100 and $200. Slavenburg believes that the integration of the piece of silicon that handles long instruction words and the complier that enables the use of long instructions will provide great flexibility in customising high performance engines for embedded control applications. Philips Components-Signetics currently has a staff of 8,000 and in 1975 became a division of the North American Philips Corp which is itself of course a wholly owned subsidiary of Philips NV, Eindhoven, Netherlands.
