MIPS Computer Systems Inc and Cadence Design Systems Inc have announced a jointly developed software design environment that will link Cadence’s CAE Verilog-XL and VHDL-XL digital logic simulators with a high performance behavioural model of the 64-bit R4000 RISC chip. The model, available from Cadence in the third quarter for Verilog-XL, will enable developers to access a register transfer-level description of the MIPS design and simulate it within the context of a complete system. The model, which MIPS will maintain to ensure compatibility, is based on a fast compiled code technology. The R4000 model and interface will be priced starting at $15,000. Availability with the VHDL-XL is scheduled to follow in the fourth quarter.
