IBM Corp revealed plans for a 500MHz bus for the forthcoming Power4 PowerPC processor at the recent Hot Chips conference. It says that current bus technology, typically running at speeds of 100MHz or 133MHz (or 200MHz in the case of Compaq Computer Corp’s 21264 Alpha bus ) isn’t sufficient to transport data from a 500-MHz plus chip to the chipset quickly enough. Using what it calls an elastic interface (more formally a synchronous wave-pipelined interface), the new design is intended to cut latency and offer data transfer synchronization. Multiprocessor designs using multiple MPU cores on the same die, will make it more important to use a high speed bus. The .18 micron Power4 is expected to include two processor cores in its initial implementation, and is expected to have a clock speed of over 1GHz (CI No 3,719).
