Motorola Inc and IBM Corp yesterday announced that the first 64-bit PowerPC processor – the 620 – has hit first silicon. It is expected to begin general sampling in the second quarter of 1995 with general availability set for the second half of 1995. The chip will initially ship running at 133MHz and the pair have taken the unusual step of specifying a maximum clock-speed design point: 150MHz. At 130MHz, the estimated SPECint92 for the processor is 225 and the SPECfp, 300. These results are for 32-bit code and the companies say that they would not expect to see a significant speed increase using the 64-bit mode. The single-chip processor contains 7m transistors, though a good proportion of these are used in the 64Kb cache, which is split evenly between data and instructions. Die size is 17.1mm by 18.2mm and programmers will be able to keep their toes warm in the long, dark winter evenings: the thing dissipates a cosy 30W at 133MHz. Perhaps the most surprising thing about the processor is the lack of a radical design change. It looks very much like an evolution of the 604. For example the 620 has exactly the same number of functional units as the 604 – three integer units (one for complex maths) one floating point unit, a branch unit and a load-store unit. The chip can fetch and dispatch up to four instructions per cycle. A little of the 620’s extra speed comes from a slightly faster transistor design, but most comes from the extra cache and a general clean-up of the functional units. The Level 2 cache controller has also come on board the processor and the designers have allowed for a massive cache capacity – it’s configurable from 1Mb to 128Mb. There has also been a substantial design push to enhance multiprocessor support, with a new method of decoupling processing from the need to check cache coherency on other processors. All in all, the designers say, this chip is designed with fast transaction processing in mind.
