Hewlett-Packard Co this week unveils the next generation of its 32-bit low-cost Precision Architecture 1.1 RISC design that has integrated multimedia functions, as the 7300LC. The 0.5 micron part will find its way into entry-level and low-end uniprocessor workstations and servers of the type currently populated by its predecessor, the 7100LC, in the second half of next year. As expected, the 7300LC will be the first Precision Architecture RISC to incorporate on-chip cache memory; the 64Kb data and 64Kb instruction caches will account for some 8m of the part’s 9m transistors. Between 512Kb and 8Mb second-level cache and up to 3.75Gb main memory (by the time systems ship) will be accessed through Hewlett-Packard’s 128-bit-wide data path. A bus converter will c urrently hook up EISA-based devices; there is apparently a PCI bridge on the way. Performance is estimated at 200 SPECint92 and 275 SPECfp92 – around the same mark as Digital Equipment Corp’s year-old, but higher-end 275MHz 21064A – or 5.5 SPECintbase95 and 7.3 SPECfpbase95, ahead of all other SPEC95 numbers so far reported bar DEC’s highest Alphas. Hewlett-Packard has kept quiet about clock frequencies, claiming cycle time numbers for DEC’s superpipelined Alpha have corrupted the marketplace, although it is understood that PA7300LC will clock at around 150MHz to begin with. There are no plans to fit PA-8000 or other non-LC Precision Architecture parts with on-chip cache.
