ARM and Cadence Design Systems have partnered to provide combined solutions for improved performance, power and time-to-market for ARM Cortex-A series processor-based system-on-chips (SoCs).
The first solution optimises ARM POP IP technology, using the Cadence Encounter digital platform, for the Cortex-A9 processor on the TSMC 40LP process, including ultra-low threshold voltage (uLVT).
The resulting solution will be available for license from ARM to speed up the implementation of ARM processors.
In the combined solution, the POP IP is coupled to Cadence Encounter RTL-to-GDSII technologies, including RTL Compiler-Physical and the breakthrough clock concurrent optimization (CCOpt) design technology.
The collaboration is being extended to the 28HPM process form TSMC and to include single, dual and quad-core implementations of Cortex-A9 and Cortex-A15 processors.
ARM vice president of marketing for Physical IP Division John Heinlein said that the company’s engagement with Cadence helps ensure that customers choosing its POP IP solutions can achieve higher performance at a lower power than previously available.
"The extensive implementation knowledge and comprehensive set of benchmarking results that ARM provides in POP technology, combined with a silicon-proven Cadence methodology, also enables customers to dramatically improve their time to market," Heinlein said.
