Mentor Graphics has announced that the Catapult C Synthesis tool has been extended to support control logic and manage low power design requirements, thus enabling full-chip high-level synthesis (HLS). The company claims that this technology allows designers to use ANSI C++ for both algorithmic blocks and control logic blocks.
The company said that extending the Catapult C tool’s capabilities to full-chip high-level synthesis is needed due to the growth in design size and complexity, which requires engineers to design hardware functionality at higher levels of abstraction.
According to the company, control logic synthesis and algorithmic synthesis have traditionally been addressed using different languages, formalisms and abstractions. The latest advances in the Catapult C Synthesis tool is claimed to unify these two domains, allowing users to describe control logic along with algorithmic behaviour leveraging ANSI C++.
Reportedly, a new C++ construct enables designers to specify asynchronous data communication, allowing control over concurrent hardware creation. This mechanism allows interfacing algorithmic representations driven by the dataflow with control-dominated blocks synchronised by clocks.
Besides, the synthesis process supports automated verification flow which lets users validate the RTL-level block interactions at the C level.
The tool has added new technology for low power design requirements by automating two prevailing design techniques: multi-level clock gating and interfacing to dynamic power and clock management units.
