Redmond, Washington-based Data I/O Corp has introduced Synario 2.0, the latest version of its Windows-based universal Field Programmable Gate Array design system, which includes optional support for the VHSIC Hardware Description Language. The VHSIC Hardware Description Language option enables design engineers to enter, simulate and synthesise Field Programmable Gate Array designs using the hardware description language in a Windows environment on a personal computer. This gives users a higher level of design abstraction and higher processor levels for all programmable devices, the company says. In addition to its Very High Density Description Language synthesis suite developed specifically for programmable logic, Synario 2.0 also includes a fully compliant IEEE-1076 simulator from Model Technology Inc that provides VHDL-based functional and timing simulation. Data I/O touts its new software as a complete PC-based VHDL solution including synthesis, simulation and source-level debugging at an affordable price. Synario’s Project Navigator simplifies the Field Programmable Gate Array design process using VHDL because it is an intelligent design-management tool, which combines built-in device knowledge with results-oriented processing, so that designers can work productively regardless of their familiarity with a device architecture or design-entry language. It also incorporates a check-list of processing steps, from entry to place-and-route. Data I/O believes that the addition of the VHDL option to Synario will increase the number of VHDL users in the Electronic Design Automation industry because the Windows-based environment makes it more user-friendly and the software and hardware are more affordable than the workstation versions that were previously needed to use VHDL. Due to ship this month, Synario 2.0 carries a price of $3,000 for the basic package and $5,000 for the VHDL option.
