In its latest edition, Microprocessor Report has compared the various superscalar architectures now on offer and concludes that the relatively conservative, partitioned approach to superscalar implementation has a clock rate advantage over the more aggressive duplicated-resource approach. The highest clock-rate designs, it says, are the 21064 (Digital Equipment Corp’s Alpha), 7100 (Hewlett-Packard Co new Precision Architecture RISC iteration), and HyperSparc (assuming Cypress Semiconductor Corp’s Ross Technology achieves its 80MHz goal). The more complex (Texas Instruments Inc) SuperSparc and (Motorola Inc) 88110 are specified for clock rates no higher than 50MHz, and SuperSparc is struggling to achieve even that. Microprocessor Report goes on to say that the clock-rate versus complexity trade-off is one of the most important issues in superscalar design, but admits that straight clock-rate comparisons of parts is only partially fair because while it is true that a more complex design, such as used in SuperSparc and the 88110, leaves less time for performance-tuning the hardware, it is also the case that clock-rate was a major focus during the design of 21064 and 7100 chips. In other words designers at DEC may have been able to make some process concessions to achieve a record clock rate that might not be appropriate for other architectures. More interestingly, the report hears that SuperSparc’s clock-rate problems are more a result of a goof in the design of the cache than of an overly complex superscalar design. The report speculates that CPUs with simpler, partitioned designs, the likes of Alpha, PA-RISC and PowerPC will be moved forward by the addition of duplicate integer units. Those that have high clock-rate designs will add more superscalar capabilities and those with high-degree superscalar implementations will be working for higher clock rates. As always, on-chip cache sizes will increase in order to keep the high-performance processor core busy.
