Synopsys Inc is reporting impressive early support for a physical synthesis tool it claims will shrink the typical place and route phase of IC design from several months, to as just a few days. SGI Inc, the graphics computer maker and fellow graphics specialist Nvidia Corp are among companies which are beta testing the Mountain View, California company’s Physical Compiler tool, which is also at the heart of a timing closure flow process under development at Hitachi Ltd’s LSI Development Center.
Place and route, the process of translating a logical design to a physical template for a new custom circuit, has become the major bottleneck to the realization of new high-speed ASIC designs. It tends to be a time consuming, iterative process, because the optimal logic designs produced by chip designers rarely map directly on to the physical layout of a chip. And, as each physical translation is returned to the logic designers for amendment, new contradictions between the physical and logical layouts are usually introduced.
Now, Synopsys claims to have decoupled the place element from place and route, and linked it directly to the logic synthesis process, so that logic designers are able to optimise logical and physical layouts almost simultaneously. Synopsys said one customer that has evaluated the new compiler shrank its graphics design cycle from three months to two days.
A number of traditional place and route tool developers are known to have been experimenting with a similar approach, but a Synopsys spokesperson claimed that the company’s expertise in logical design has given it the edge. The nearer you are to the original design process, the easier it is for you to effect fundamental changes like this said a Synopsys spokesman. He added that with 90% of the logic synthesis market under its influence, the company expects its new approach to catch on quickly with ASIC designers.
The early support of SGI and Nvidia suggests that Synopsys is on to something, and could spread its design reach out of its traditional synthesis stronghold. However, the spokesperson said that although it is no secret that Synopsys is moving into the physical side of chip design, the Physical Compiler is not intended as a direct challenge to place and route tool makers. Instead, the product is written to pass placement data to routing tools of third parties.
Synopsys said Physical Compiler is still only available under restricted release conditions, but a commercial launch can be expected soon.
