Technology and services company Texas Instruments and communications software developer Aricent have said they collaborated on a small cell protocol stack optimised for TI’s KeyStone-based multicore System-on-Chips (SoCs).
The integrated applications from TI and Aricent enables developers to design small cell base stations and these small cell protocol stack is designed for users of TI’s KeyStone-based multicore processors and SoCs.
TI’s scalable KeyStone architecture includes support for both TMS320C66x digital signal processors (DSP) generation cores and multiple cache coherent quad ARM Cortex-A15 clusters, for a mixture of up to 32 DSP and RISC cores.
TI’s KeyStone architecture also includes offloaded, flexible packet and security coprocessors and capacity expansion for SoC structural elements such as TeraNet, Multicore Navigator and Multicore Shared Memory Controller (MSMC).
The SoC structural elements provide integration between the DSP and ARM RISC cores, allowing base stations developers to utilise the capability of all processing elements, including the cores and enhanced AccelerationPacs.
