Intel Corp and its co-partner Hewlett-Packard Co are set to reveal the IA-64 instruction set today, in an announcement that has been widely leaked around the internet over the last few days. Intel’s announcement is expected to concentrate only on information about the instruction set and architecture that application programmers need to know, and will co-incide with the publication of a number of programmer manuals that will be available for downloading from the company’s web site. The guides will list the 148 IA-64 instructions in detail.
Styled as the biggest disclosure since the X86, the new details will reveal an architecture which, according to Intel, will get round some of the limitations of current RISC architectures by using the EPIC instruction set, which uses such techniques such as explicit parallelism, predication and speculation. Intel and HP will detail a 128 register architecture – compared to the Pentium’s eight registers and the PA-RISC’s 32 – a high performance floating point architecture, support for existing multimedia instruction sets from both companies, and sophisticated memory management and 64-bit addressing. It will claim that those features will make the chip suitable for running internet, e-commerce, financial and scientific applications, according to some reports.
Both Intel and HP are expected to detail compatibility with previous architectures. While Intel has embedded support for its 32-bit line of processors using a different instruction decoder, HP has developed dynamic translation technology for PA-customers wanting to run their old applications on the new generation of servers.
There is not likely to any further news on IA-64 availability. Intel won’t comment on whether chip has reached the tape out stage, although the first samples are expected to be shipped to OEMs in a few months time. Until then, OEMs must make do with the IA-64 simulator Intel has already released.
