The 4Gb DRAM has a capacity of 4.29 billion bits. A single chip can store the data equivalent of 32,000 standard newspaper pages, 1,600 still photographs or 64 hours of recorded audio. This sophisticated device is well suited for use as the main memory for high-performance servers.
By applying 0.10-micron design rule to the 4Gb DRAM, circuits are just one one-thousandth the thickness of a human hair. Core technologies required for such high precision processing include high-resolution lithography, the capability to secure static electricity capacity in the chip cells and low-resistance circuitry.
Through the development of the technology for 4Gb DRAMs, Samsung secured the following new semiconductor technologies:
fine circuitry by utilizing Gain Controlled Pre-Sensing (GCP),
stable circuitry by applying Reference Bit-Line Calibration (RBC),
and a variety of design technology, including the chip operation capability at 1.8V, that can respond to the market’s demand for low-voltage chips and more advanced processing technology.
Samsung selected the 16-bit data input/output structure and integrated the design technology of double data rate (DDR) and single data rate (SDR) chips.
Samsung officials say that applying the new 0.10-micron design rule to the 256Mb and 128Mb DRAM chips currently under production will lower production costs by at least 60%. Thus, the company will secure a stronger price competitiveness in the marketplace.
Samsung Electronics has applied for more than 140 domestic and foreign patents related to 4Gb DRAM technology during the development process of its 0.10-micron technology. The company is expected to obtain patents for technologies essential for the mass fabrication of next-generation memory devices, which could bring royalty income to the company.
On February 7, Samsung Electronics presented a paper on its technology at the International Solid-State Circuits Conference (ISSCC) in San Francisco. The ISSCC is the world’s most prestigious academic conference for the semiconductor industry.
