Cadence has expanded its technology partnership with Nvidia, aiming to accelerate agentic AI, physics-based simulation, and digital twin solutions for engineering and system design.
The announcement was made during CadenceLIVE Silicon Valley 2026, underlining the companies’ plan to increase productivity in semiconductor design processes, physical AI system development, and AI factory deployment.
Cadence president and CEO Anirudh Devgan said: “Agentic AI and digital twins are reshaping the entire engineering landscape—from semiconductor design to planetary‑scale AI systems.
“Our expanded collaboration with Nvidia accelerates the convergence of design and physical realisation, connecting the Cadence AgentStack, Physical AI Stack, and AI factory digital twins with Nvidia’s breakthroughs in accelerated computing to deliver unprecedented speed, accuracy and trust in simulation and system development.”
Cadence plans to integrate its electronic design automation (EDA) and system design and analysis (SDA) capabilities with Nvidia’s CUDA-X libraries, AI physics models, and Omniverse simulation platforms.
The company’s Millennium M2000 Supercomputer, powered by Nvidia’s AI infrastructure, forms part of the hardware stack underpinning this collaboration.
Cadence stated that by leveraging these combined resources, engineers could expect up to a 100-fold speedup in various computational workflows, especially in complex simulation and verification tasks that are critical to chip and system development.
The company’s EDA and SDA clients, including entities like Ascendence, Argonne National Laboratory, Honda R&D, Samsung, and SK Hynix, are already said to be utilising solutions based on Nvidia technologies to reduce product development cycles.
Nvidia founder and CEO Jensen Huang said: “We are at an inflection point in computing—CUDA-accelerated computing and AI are reinventing the engineering process.
“For the first time, we can innovate in the digital world—exploring, testing, and optimising ideas at unprecedented speed and scale—by building everything as full-fidelity digital twins first. Together, Nvidia and Cadence are bringing this vision to life—transforming how engineers design, build and operate the world.”
A recent step in Cadence’s product roadmap is the introduction of its ChipStack AI Super Agent, designed to automate semiconductor RTL design and verification by combining agentic AI with Cadence’s core EDA tools.
Building further, Cadence unveiled AgentStack, a coordinating agent intended to handle all facets of semiconductor and system design, from RTL through verification, physical, analogue, and system-level design.
AgentStack links together Cadence agents and EDA platforms operating on Nvidia’s accelerated computing stack and utilises Nvidia Nemotron for running multi-agent design workflows.
Outside the core domain of semiconductor development, the partnership between Cadence and Nvidia is extending to embedded agentic AI for real-world applications such as robotics and autonomous systems.
Cadence’s Physical AI Stack will integrate with Nvidia’s simulation libraries, including Isaac open-source packages and the Cosmos open-world modelling toolkit.
Customers can then deploy agent-orchestrated, closed-loop workflows that cover data-driven training, physics-based validation, scenario simulation, and real-time deployment feedback. These workflows are deployable to Nvidia Jetson robotics and edge AI frameworks, supporting continuous experimentation and refinement in production environments.
In hyperscale AI factory contexts, Cadence integrates Nvidia Omniverse DSX Blueprint to support digital twin creation and optimisation for large-scale systems. This solution is designed for users to model energy efficiency metrics such as tokens processed per watt, with the joint companies simulating variations in GPU power settings, cooling architectures, and overall data centre layout.
Additionally, Cadence made public a strategic collaboration with Google to optimise the Cadence ChipStack AI Super Agent stack using Gemini on Google Cloud. This effort focuses on cloud-native, scalable, agent-driven automation supporting advanced chip design and verification workflows.
