Along with a paper on Matsushita’s 64-bit Sparc implementation (CI No 1,365), attendees at the San Francisco ISSC Conference held this week have been hearing details of a new high speed CMOS version of Hewlett-Packard’s Precision Architecture RISC chip. A slower version of the part – rated at between 50 and 60 MIPS and 12 to 16 MFLOPS (CI No, 1,324). is due to appear in the recently announced top-end HP3000 980/100 and 200 machines announced in January, available by the end of this year (CI No 1,340). The new part, which runs at a blinding 90MHz under typical conditions, implements Hewlett’s existing set of 140 instuctions, and will be used, like its predecessor, in workstations and technical and commercial multi-user systems, where sustained performance is required. Hewlett claims to achieve performance comparable with many ECL implementations by including features such as a 3nS 32-bit adder, low skew on-chip clock buffers, and cycling off-chip caches using industry standard statics at the operating frequency. The chip includes an integer fetch and execute unit, instruction and data translation lookahead buffers (each with two way 64 entries), a control unit for the off-chip instruction and data writeback caches, full multi-processing support hardware, a performance analysis and tuning interface, and tightly coupled co-processor interface. Costs were reduced by using standard cell control blocks, library based datapath and programmed logic arrays, and autorouting, with full custom design limited to the arithmetic-logic unit, clocks and input-output circuits. The CPU uses a 64-bit virtual address to drive data to the two-way instruction and data caches, which are configurable with up to 2Mb each: the instruction cache is 32 bits wide (plus parity) each way, while the data cache is 64 bits wide each way (plus error-correcting code). Only 32-bits of the data cache are sent to the CPU, while all 64-bits are sent to the floating point unit, allowing single cycle execution of double word floating point load/store instructions. The chip has a five stage pipeline: instruction fetch, operand read, execute, memory access, and register write. Hewlett claims that the chip has now been successfully fabricated, booted multiple operating systems on first silicon, and runs existing software from previous implementations of the Spectrum RISC Precision Architecture.
