Taiwan Semiconductor Manufacturing Company (TSMC) has introduced 65-nanometer (nm) multi-time programmable (MTP) non-volatile memory (NVM) process technology. The technology incorporates process-qualified MTP IP blocks, jointly developed with Virage Logic. Reportedly, the new technology is a 2.5 volt MTP process which eliminates the need for an external EEPROM for systems applications.
TSMC claims that the new MTP technology, built on its 65nm Low Power (LP) process, features up to 8k bits memory size that is suited for small memory requirements associated with MP3 music downloadable digital rights management, RFID devices, fingerprint identification applications and pre-paid cash or phone cards.
According to the company, the 65nm MTP process is built up to 10 metal layers using copper low-k interconnects and nickel silicide transistor interconnects. The technology is claimed to be logic-compatible and the NVM memory reportedly requires no additional processes or masks. Devices designed using the process are expected to support read and programme operations across temperatures ranging from -40 degrees C to 125 degrees C, with minimum 10-year data retention at 125 degrees C.
The company’s 65nm node is also expected to support embedded DRAM option found in consumer applications and in small form factor handheld devices.
The company said that all its 65nm processes are supported by the company’s Design Support Ecosystem featuring DFM-compliant products and services, by TSMC Reference Flow design methodology, and by a variety of process-proven TSMC and third party IP libraries including a memory compiler, I/O and standard cell libraries.
