In Texas, down in leafy Austin, IBM Corp has a detailed road map for the future of the RS/6000 Unix processor, and with all the talk of late being of super-low-end machines, the company is at pains to remind people that the road map does not lay out a one-way street, it extends in both directions. Those that follow these things closely will be aware that early 1992 will see not only the launch of new low-end RS/6000s, but new high-end models as well – and those machines are just the beginning. The RT fiasco was a big setback in IBM’s campaign to be recognised as a leading edge Unix systems vendor, but it did give the company one clear advantage: the Rios processor was designed so late in the day that it is still free of the baggage that is already beginning to weigh down MIPS Computer Systems Inc’s R-series RISC and even Sparc.

Spanish moss

So that while the first reaction to Phil Hester, vice-president, systems and technology in the Advanced Workstations Division, saying that Sparc and R-series will not be able to keep up at the top end is the kneejerk He would say that, wouldn’t he, the claim is probably justified. And just as the 80586 will be trammelled with 80386 and even 8086 baggage, Hester admits that by the end of the decade, the Rios processor too will begin to be festooned with as much Spanish moss as the trees in the Texas swamps; in the meantime there is a decade of welcome freedom for IBM’s chip designers. Hester declares that the only mission of his division is to make IBM successful in the Unix business that means being one or two in the market by 1993 or 1994 – with no power of price constraints. That implies that if the market demands an RS/6000 that outperforms a Summit in many applications, then such a machine will be offered: sounds fine for now, but we’ll see when the time comes. IBM is constantly surprised at the extent of commercial market demand for Unix, and so the RS/6000 business is already split 50-50 between technical and commercial, and it is becoming clear that, just as with the minicomputer business in the mid-1970s, the commercial end of the market is embarking on a much steeper growth curve than the technical. And from IBM, we can expect to see some RS/6000 models optimised for floating point performance – as the machine essentially is now, and others optimised for transaction processing. And optimisation may extend to adding different instructions to the set according to the intended use. Talk of extending the instruction set will upset purists that say that with 184 or so instructions, the Rios can scarcely be called a RISC anyway, but as the inventor and holder of all the early patents on RISC, IBM begs leave to define the term as it chooses, so in IBM parlance, RISC stands for Reduced Instruction Set Cycles, and the design aim is to optimise the machine to execute as many instructions as possible. Just as a few 16-bit minicomputer designers realised that 32-bit would be needed one day and designed their machines so that the bus and register size could be doubled when the time came, as Honeywell Inc did with DPS 6, while others had to start virtually from scratch with the VAX or the MV/8000, so IBM has designed the Rios with 64-bit in mind, so that there will be a 64-bit RS/6000 for mid-decade.

Livermore

The machine currently spans the $15,000 to $150,000 price range, but will extend – equally fast – in both directions, so we can look forward, says Hester, to a future high-end machine costing $1m or so, which will offer symmetric multiprocessing on 64-bit CPUs for the commercial market, and will be able to be clustered for the scientific world. How far will multiprocessing go? We’re not talking massive parallelism with the RS/6000: the answer is from four-way to 16-way, after which clustering will be required for even bigger configurations – and a fibre optic channel standard is in development at one or two of the US national laboratories to enable clusters to operate at extremely high speeds – 100M-bytes per second or more; Lawrence Livermore National Laboratory is already u

sing a 25.25Mbyte-per-second link between its RS/6000s. So what is on the cards in the performance stakes? Raw processor performance, says Hester, can double every 12 to 16 months, so by 1993, a five-to-eightfold increase is realistic. At present, the machine is a uniprocessor with one integer and one floating point unit delivering two operations per cycle and one branch per cycle – 100 to 150 million operations per second, 72 SPECmarks, 50 or more transactions per second. Performance can be improved not only by winding up the clock – and 60MHz next year, 100MHz in 1993 are on the cards. It is not exactly a new trick to increase the number of integer and floating point units within the CPU and split the instruction stream between them – ask Prime Computer Inc or Tandem Computers Inc. The number of Optimised compilers can improve performance by 50% – and IBM is doing its own compilers for the major languages. Symmetric multiprocessing can create configurations two to 10 times as powerful as the uniprocessor – within one or two years. And clustering can give a 100-fold increase in performance, so that 10,000 times today’s performance will be available. And to underline the scope of the design, it has a 52-bit virtual address – 4 Petabytes consisting of 16m 256Mb segments; on the other hand, input-output is handled by off-the-shelf 80186-type processors – sounds like the NEC Corp V40. The machine presently uses a 40Mbyte-per-second Micro Channel bus, twice as fast as in the PS/2, but at the high end, 80M-bytes-per-second – 8 bytes at 100nS, and even 160Mbps, 8 bytes at 50nS, are likely to be needed.

Video bus

At the chip level, implementation will be in CMOS or BiCMOS for the foreseeable future – after all, you reckon to get twice the performance for a given set of design rules with RISC as you do with a complex instruction set microprocessor, and one of the ways IBM was able to get the Rios out the door in what for IBM was a timely fashion was by eschewing custom logic for standard cells wherever possible: the trade-off is in raw performance against time-to-market. With the single chip implementation, the company has had to use rather more custom logic. So what about the low end? We’re talking of something in the $5,000 to $10,000 price range next year, but the future low-end machine is an object-based multimedia personal workstation – that will require a video bus in addition to the Micro Channel. And yes, there will be an RS/6000 laptop, but despite the pioneering machines in the market, IBM doesn’t believe that the technologies are there yet: it reckons that a Unix lap-top needs a 1,024 by 768 pixel colour screen and a 150Mb to 300Mb disk drive, so we have to look out to around 1993 before we see a Unix laptop in IBM colours – but don’t doubt that such a machine is in the plan. That then – subject to change according to circumstances, is IBM’s current RS/6000 road map.