Working towards the development of 256M-bit dynamic memory chips, NEC Corp scientists have developed what they claim is the world’s smallest electronic cell with a surface area of just 0.54 square microns. The new technology was made possible by the development of Split-Level Diagonal Bit-line, which allows for the construction of circuitry on a two level bit-line, thus saving space; a new form of trench isolation technology in which a buried oxide in the shape of an inverted triangle allows smooth operation at the 256M-bit level; and a cylindrical capacitor which uses hemispherical grained silicon – HSG-Si. To achieve 256M-bit capacities, at minimum 0.25 micron design rules will be required. Meantime NEC is increasing its production of the present generation 16M-bit memory chips by more than 500% as of early 1994. The company has been making about 300,000 16Ms a month and NEC said that figure will easily climb higher than 2m chips a month with added production from the California factory and a new facility under construction in Japan. The company expects to invest $200m in plant and equipment at the new Japanese wafer fab before its opening in early 1994. The company is already seeing substantial demand from the workstation industry – RISCs need much more memory to work at full efficiency – and forecasts that demand will soar.
