Hewlett-Packard Co has confirmed that the agreement to merge the Precision Architecture RISC microprocessor architecture with Intel Corp’s iAPX-86 will start with its PA 9000, which is not due before 1997, and Intel Corp’s P7. The CPU will be released in different iterations for different machines scaling from personal computers to mainframes, and will be fabricated in new jointly built and operated facilities working to 0.25 micron design rules. However the location has not been decided yet, nor has the name of the new processor. Hewlett-Packard reckons that it will be another couple of months before specific details are decided upon, but promises that these will be made available by the end of the year. Nonetheless, the firm believes that many of the instructions necessary for parallel execution will not be included in the chip – parallelism will instead be undertaken by the Very Long Instruction Word Trace compilers that Hewlett-Packard inherited from Multiflow Computers Inc. Hewlett-Packard believes this will take the chip beyond the traditional four-way superscalar limitations of RISC, enabling it to add more pipelines. The processor is also likely to have between two and four times the 3m transistors currently found in the 7100LC. Meanwhile the PA 8000, scheduled for release in 1995, is expected to provide between two and four times the performance of the 7150LC, and will be initially fabricated to 0.5 micron design rules. This will be reduced to 0.35 micron over time.
