The IBM Corp-Motorola Inc Somerset team this week unveils the PowerPC 620 as its first 64-bit part, designed from the ground up as a building block for high-end multiprocessing systems that will run 32-bit PowerPC binaries unchanged. The single-chip unit, which will clock at 133MHz rising to 150MHz in subsequent iterations, is estimated initially at 225 SPECint92 and 300 SPECfp92. Somerset, which claims it’s got first 620 silicon in-house but that it’s too early to estimate yields, says general sampling will begin second quarter 1995 with volume in the second half. The 167MHz 64-bit UltraSparc starts at 250 SPECint92 and 310 SPECfp92 and is expected in volume by mid-1995. Somerset says the 620 will best whatever Intel Corp can achieve with its next-generation, dual-chip P6. Fabricated in 0.5 micron, four-layer metal CMOS by IBM in Burlington, Vermont and Motorola in Austin, Texas, PowerPC 620 has some 7m transistors, dissipates 30W and measures 311 square millimetres. It includes 32Kb data and instruction cache and on-chip secondary cache control. The superscalar part can issue up to four instructions in parallel every clock cycle, performs some speculative execution, bus snooping and has six execution units; branch, three integer, floating point and load-store. It therefore has just one more integer unit than Somerset’s previous design, the 604. Like the latest Sparc and MIPS parts, the 620 has an all-new 128-bit bus claimed to pass data at a peak rate of 1Gbps. Bridge processors will support PCI bus. It is seen primarily for use in two-to-eight-way systems. Compagnie des Machines Bull SA is already working on Mississippi clustering technology for 620-based systems and Somerset claims other design wins too. Somerset will shrink its 5L PowerPC process to a five-layer VDR85 method with faster transistors; it is looking at very long instruction word technology for the future.
